Sources related to the subject of EAIC systems discussed in this text.Important historical contributions to asynchronous circuit synthesis.Alternative approaches to asynchronous state machine design and analysis.
General background directly supporting material in this text.
Serial parallel converter circuit fsm software#
Serial parallel converter circuit fsm mac#
Time-shared FSM operation by using cascaded MAC modules.Programming the MAC module, four examples.MAC module characteristics for use with CAPS system architecture.Microprogrammable asynchronous controller modules.Cascadable asynchronous programmable sequencers (CAPS) and time-shared system design.Summary of the salient features of EAIC systems.Parallel/serial processing with cascaded EAIC microcontrollers.Frequency characteristics and NS logic constraints of EAIC systems.DFLOP memory element design with C-elements.Basic architecture and system characteristics.Externally asynchronous/internally clocked systems.Self-timed systems, programmable sequencers, and arbiters.E-hazard and D-trio analyses of the PGM.Procedure for analyzing any asynchronous FSM.Other memory elements suitable for pulse mode design.Requirements and characteristics of the pulse mode approach.Models and characteristics of the pulse mode.Essential hazards in one-hot asynchronous FSMs.Summary of hazard effects and their elimination in STT FSM designs.Design of single transition time machines.Minimum requirements for E-hazard and D-trio formation.Essential hazards, detection and elimination.Output race glitches, detection and elimination.Detection and elimination of static hazards in the output forming logic.Detection and elimination of static hazards in the NS forming logic.Static hazards in the NS and output forming logic.Detection and elimination of timing defects in asynchronous FSMs.Sanity circuits, design and applications.